TY - GEN
T1 - Realization of 4D lattice-ladder digital filters
AU - Kousoulis, M. T.
AU - Antoniou, G. E.
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/4/11
Y1 - 2016/4/11
N2 - A circuit realization is presented for four-dimensional (4D) lattice-ladder discrete filters. The proposed 4D circuit realization requires, for its implementation, a minimum number of delay elements. Further, the dimension of the state-vector, of the derived 4D state-space model, is minimal and its 4D transfer function is characterized by the all-pass property. A step-by-step low-order example is provided to demonstrate the proposed minimality of both, circuit, and state-space realizations. An educational conjointment of 4D lattice filters with lower dimension filters (2D, 1D), is imparted.
AB - A circuit realization is presented for four-dimensional (4D) lattice-ladder discrete filters. The proposed 4D circuit realization requires, for its implementation, a minimum number of delay elements. Further, the dimension of the state-vector, of the derived 4D state-space model, is minimal and its 4D transfer function is characterized by the all-pass property. A step-by-step low-order example is provided to demonstrate the proposed minimality of both, circuit, and state-space realizations. An educational conjointment of 4D lattice filters with lower dimension filters (2D, 1D), is imparted.
UR - http://www.scopus.com/inward/record.url?scp=84982810899&partnerID=8YFLogxK
U2 - 10.1109/LASCAS.2016.7450998
DO - 10.1109/LASCAS.2016.7450998
M3 - Conference contribution
AN - SCOPUS:84982810899
T3 - LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
SP - 15
EP - 18
BT - LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
A2 - Andreou, Andreas G.
A2 - Julian, Pedro
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016
Y2 - 27 February 2016 through 1 March 2016
ER -