Realization of 4D lattice-ladder digital filters

M. T. Kousoulis, G. E. Antoniou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A circuit realization is presented for four-dimensional (4D) lattice-ladder discrete filters. The proposed 4D circuit realization requires, for its implementation, a minimum number of delay elements. Further, the dimension of the state-vector, of the derived 4D state-space model, is minimal and its 4D transfer function is characterized by the all-pass property. A step-by-step low-order example is provided to demonstrate the proposed minimality of both, circuit, and state-space realizations. An educational conjointment of 4D lattice filters with lower dimension filters (2D, 1D), is imparted.

Original languageEnglish
Title of host publicationLASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
EditorsAndreas G. Andreou, Pedro Julian
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages15-18
Number of pages4
ISBN (Electronic)9781467378352
DOIs
StatePublished - 11 Apr 2016
Event7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 - Florianopolis, Brazil
Duration: 27 Feb 20161 Mar 2016

Publication series

NameLASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference

Other

Other7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016
CountryBrazil
CityFlorianopolis
Period27/02/161/03/16

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Kousoulis, M. T., & Antoniou, G. E. (2016). Realization of 4D lattice-ladder digital filters. In A. G. Andreou, & P. Julian (Eds.), LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference (pp. 15-18). [7450998] (LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS.2016.7450998