Verification method for area optimization of mixed-polarity Reed-Muller logic circuits

Keyphrases

• Verification Method 100%
• Area Optimization 100%
• Logic Circuit 100%
• Mixed Polarity Reed-Muller 100%
• Reed-Muller Logic 100%
• Design Compiler 66%
• Electronic Design Automation Tools 50%
• Discrete Particle Swarm Optimization 50%
• Intelligence Algorithm 33%
• Optimization Approach 16%
• Area Minimization 16%
• SA-PSO 16%
• Logic Gates 16%
• Benchmark Circuits 16%
• Combinational Logic Circuits 16%
• Logic Synthesis 16%
• Hybrid Simulated Annealing 16%
• Artificial Intelligence Algorithm 16%

Engineering

• Derjaguin-Muller-Toporov Model 100%
• Logic Circuit 100%
• Particle Swarm Optimization 50%
• Electronic Design Automation 50%
• Illustrates 16%
• Optimization Approach 16%
• Logic Gate 16%
• Logic Synthesis 16%
• Artificial Intelligence 16%