Verification method for area optimization of mixed-polarity Reed-Muller logic circuits

Keyphrases

• Verification Method 100%
• Area Optimization 100%
• Logic Circuit 100%
• Mixed Polarity Reed-Muller 100%
• Reed-Muller Logic 100%
• Design Compiler 66%
• Electronic Design Automation Tools 50%
• Artificial Intelligence Algorithm 50%
• Discrete Particle Swarm Optimization 50%
• Area Minimization 16%
• SA-PSO 16%
• Logic Gates 16%
• Benchmark Circuits 16%
• Hybrid Simulated Annealing 16%
• Particle Swarm Optimization Algorithm 16%
• Logic Synthesis 16%
• Combinational Logic Circuit 16%

Computer Science

• Compiler 100%
• Electronic Design Automation 75%
• Automation Tool 75%
• discrete particle swarm optimization 75%
• Simulated Annealing 25%
• Artificial Intelligence 25%
• Logic Gate 25%
• Logic Synthesis 25%
• Combinational Logic 25%
• Benchmark Circuit 25%